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05386026
- In a series of papers in recent years new structures for coherent M-PSK (M-ary Phase Shift Keying) receivers were suggested. These include structures for carrier phase detectors for the carrier PLL (Phase Lock Loop), carrier PLL lock dete
resonant-frequency-testing
- 通过labview控制信号发生器和锁相放大器进行共振频率检测的程序。freq test.vi实现信号发生器的频率扫描，lockin test.vi 实现锁相放大器的参数设定，数据采集.vi实现锁相数据的采集，waveform arrays to file实现波形数据到文件数据的转换。共振频率测试.vi实现晶振等共振频率的测试-Resonance frequency detection procedures performed by labview control signal generator
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
aaa
- 一种全数字时钟数据恢复电路的设计与实现，提出一种改进型超前滞后锁相环法的全数字时钟恢复算法，与同类电路比较，具有数据码率捕获范围宽、捕获时间短的优点。-Clock Date Recovery(CDR)circuit is a important part of data transmission equipment．For the burst data transmission，the traditional phase—lock loop can hardly achieve the re
FLL_PLL_demo
- Demo that shows how Phase Lock Loop and Frequency locked loop works.
sanxiangsuohuan
- 三相锁环模型，这个模型可以直接用，很方便。-Three phase lock ring model, this model can be used directly, very convenient.
PLL
- 基于simulink的三相PLL锁相环仿真,可以直接使用-Three phase PLL phase lock simuliation，it can be used directly
commfreqsyn
- 锁相频率合成器的simulink模型，可验证电路设计的工作过程和合理性。-Phase lock loop
three_phase_harmonics_pll
- 三阶锁相环频率合成器的simulink 模型，可以演示三阶锁相环工程过程，验证参数合理性-Three phase lock loop
plltest
- 基于Dq变换数字实现三相锁相环的功能，对于谐波的抗干扰能力差-three-phase phase-lock loop based on d-q transformation
PLL_1
- Phase lock loop generation for vhdl (DE2 board)
lock-in_amplider
- 锁定放大器是利用相关技术从噪声中提取微弱信号的常用方法之一。可以证明，当信号的频率和相位已知时，使用相关检测技术能使输出信号信噪比最大。数字锁定放大器比模拟锁定放大器具有稳定、精度高等优点，并且数字滤波器的通带可以设置的非常窄，以便滤除噪声。-Lock-in amplifier is a common method using correlation techniques extracting weak signals the noise in. It can be shown when th
PLL1
- 锁相环跟踪主程序，里面有参数的详细说明,适合初学者理解锁相环的跟踪过程-simulation code for phase lock loop
pll
- A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circu
digitai-signal
- 基于FPGA的锁相环，可用于提取同步信号-FPGA based phase lock loop, which can be used to extract the synchronous signal
pll
- Phase lock loop presentation
the-inverter-control-based-on-SVPWM
- 用simulink建立的逆变器模型，主要包括坐标变换模块、锁相模块和SVPWM控制模块，可以根据需要设置参数和调节功率因数。-The inverter model, which is built by Simulink, mainly includes coordinate transformation module, phase lock module and SVPWM control module, which can set parameters and adjust power fac
PLL.plecs
- PLECS是一个用于电路和控制结合的多功能仿真软件，尤其适用于电力电子和传动系统。这个PLECS模块是一个锁相环（这个软件没有自带锁相环），这个锁相环是照着MATLAB底层文件搭建的-PLECS is a versatile simulation software for circuit and control, especially for power electronics and transmission system. This PLECS module is a phase locke
pllddsrf3191
- 论述了风力发电并网的PLL技术，基于传统PI-PLL技术基础上，以双同步旋转坐标系建立电网电压不平衡的数学模型。-mbalance of power grid voltage phase lock loop
virtualPLL
- virtual phase lock loop p-virtual phase lock loop pll